50-100 µm deep, Fluorine Etch in Si,
SiO2 mask not removed
The lower SEM shows the "microloading effect"
at room temperature, (Courtesy of IMO, Wetzlar)

Plasmalab 80 Plus

RIE Results:
Isotropic Etch
Rate : up to 4 µm / min
Uniformity: < +/- 5 % (4")
Mask: SiO2

RIE technology

ICP :Rapid lateral etch
high selectivity over SiO2
process gases: SF6/O2
vertical depth: 20µm
lateral undercut: 50µm per side
lateral Si etch rate: 1.8µm/min (2x3cm chip)
selectivity Si:SiO2 > 650:1
(results with ICP65)

Room temperature process
used to suspend the CMOS active
device by removal of epi-silicon.

Plasmalab System 100

ICP RIE technology