Courtesy of Infineon:
0.15 µm SiN low damage spacer etching

System 100 cluster
with 2 ICP sources

ICP RIE technology

Courtesy of Infineon:
0.15 µm SiN low damage spacer etching

first process step for excellent uniformity at ca 80 Volt

second process step for very low damage ca 5-20 Volt

uniformity  < ± 2  % (100 mm wafer)

The ICP technology has replaced the ECR technology
used here originally in 1994 - 1997, see ICP vs ECR.